As a data processor (a built-in processor) incorporated into an apparatus which needs to have high efficiency, a RISC (Reduced Instruction Set Computer) type built-in processor is widespread. The RISC type is a 16-bit fixed-length instruction set by which high code efficiency can be realized. Even at the present time, in which memory capacity has advanced, high code efficiency is indispensable in effectively utilizing on-chip cache, RAM or ROM. However, with the 16-bit fixed-length instruction set, a program size can be decreased, but the number of instructions is increased. Specifically, due to a restriction on operand designation, the number of move instructions between registers and move immediate instructions is increased. The increase in the number of instructions is a cause of a decrease in performance and of an increase in power consumption.
This problem occurs because an instruction code space of the 16-bit fixed-length instruction set, 216=64 k patterns, is considerably small, compared to an instruction code space of a 32-bit fixed-length instruction set, 232=4 G patterns. Because of this, for example, a data processor is provided in which the instruction code space is broadened by mixing the 16-bit fixed-length instruction and the 32-bit fixed-length instruction. On the other hand, in the processors in PTL 1 and PTL 2, the instruction code space is broadened by a 16-bit prefix to the 16-bit fixed-length instruction set. In PTL 3, a method is disclosed in which superscalar execution is realized in the instruction set including the 16-bit prefix.